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P-N junction

P-N junction

A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...

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Related Experiment Video

Updated: Jun 6, 2025

Electric-field Control of Electronic States in WS2 Nanodevices by Electrolyte Gating

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Superior P-Type Switching in InSe Nanosheets for Complementary Multifunctional Systems.

Minsu Kim¹, Dongju Yeom¹, Yongwook Seok¹

¹School of Electrical Engineering, Korea Advanced Institute of Science & Technology (KAIST), Daejeon 34141, Republic of Korea.

|November 25, 2024

Summary

This study demonstrates ambipolar indium selenide (InSe) transistors with tunable p-type and n-type behavior. These devices enable reconfigurable complementary logic and tunable rectifiers without complex doping or heterostructures.

Keywords:

ambipolar indium selenide multifunctionality p-type van der Waals contacts

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Area of Science:

Materials Science
Condensed Matter Physics
Nanotechnology

Background:

Van der Waals (vdW) indium selenide (InSe) exhibits high electron mobility and a moderate band gap.
The intrinsic n-type conductivity of InSe limits its application in complementary circuits.
Developing InSe for both n-type and p-type devices is crucial for advanced electronics.

Purpose of the Study:

To engineer ambipolar indium selenide (InSe) transistors.
To achieve high performance p-type characteristics in InSe devices.
To demonstrate reconfigurable multifunctional devices based on InSe.

Main Methods:

Fabrication of InSe transistors with van der Waals (vdW) bottom contacts.
Implementation of a partially gate-coupled architecture.
Electrical characterization of transistor performance, including on/off ratios and Schottky barrier heights.

Main Results:

Achieved superior ambipolar InSe transistors with p-type on/off ratios exceeding 10^9.
Demonstrated gate-tunable rectification polarity and ratio (from 3.5 x 10^7 down to ~10).
Showcased reversible, electrically tunable breakdown voltages and switching ratios exceeding 10^8.

Conclusions:

Partially gate-coupled architecture enables ambipolar InSe transistors and reconfigurable complementary multifunctionality.
Gate-tunable rectification and breakdown characteristics are achieved without complex doping or heterostructures.
This work expands the application scope of InSe for advanced integrated microsystems.