Si Characterization on Thinning and Singulation Processes for 2.5/3D HBM Package Integration

As stacking technologies, such as 2.5D and 3D packages, continue to accelerate in advanced semiconductor components, the singulation and thinning of Si wafers are becoming increasingly critical. Despite their importance in producing thinner and more reliable Si chips, achieving high reliability remains a challenge, and comprehensive research on the effects of these processing techniques on Si chip integrity is lacking. In this study, the impacts of wafer thinning and singulation on the fracture strength of Si wafers were systematically compared. Three different grinding processes, namely fine grinding, poly-grinding, and polishing, were used for thinning, and the resulting surface morphology and roughness were analyzed using scanning electron microscopy and an interferometer. In addition, the residual mechanical stress on the wafer surface was measured using Raman spectroscopy. The fracture strength of Si wafers and chips was assessed through three-point bending tests. Singulation, including blade dicing, laser dicing, and stealth dicing, was evaluated for its impact on fracture strength. Among these processes, polishing for wafer thinning exhibited the lowest full-width half maximum and intensity ratio of Raman shifts (I480/I520), indicating minimal residual stress and surface defects. Consequently, Si wafers and chips processed through polishing demonstrated the highest fracture strength. Moreover, the 60 µm thick Si wafers and chips showed the highest fracture strength compared with those with thicknesses of 90 and 120 µm, possibly because of the increased flexibility, which mitigates stress. Among the singulation methods, stealth dicing yielded the highest fracture strength, outperforming blade and laser dicing. The combination of wafer thinning via polishing and singulation via stealth dicing presents an optimal solution for producing highly reliable Si chips for 2.5D and 3D packaging. These findings may be valuable in selecting optimal processing technologies for high-reliability Si chip production in industrial settings.