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Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

Ampere-Maxwell's Law: Problem-Solving

Ampere-Maxwell's Law: Problem-Solving

A parallel-plate capacitor with capacitance C, whose plates have area A and separation distance d, is connected to a resistor R and a battery of voltage V. The current starts to flow at t = 0. What is the displacement current between the capacitor plates at time t? From the properties of the capacitor, what is the corresponding real current?
To solve the problem, we can use the equations from the analysis of an RC circuit and Maxwell's version of Ampère's law.
For the first part of...

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Updated: Jun 5, 2025

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Large Scale Energy Efficient Sensor Network Routing Using a Quantum Processor Unit

Published on: September 8, 2023

A large scale photonic matrix processor enabled by charge accumulation.

Frank Brückerhoff-Plückelmann^1,2, Ivonne Bente^3,2, Daniel Wendland^3,2

¹Department of Physics, University of Münster, CeNTech, Heisenberg Str. 11, 48155 Muenster, Germany.

Nanophotonics (Berlin, Germany)

|December 5, 2024

Summary

This summary is machine-generated.

Researchers developed a time-multiplexed photonic circuit for artificial neural networks (ANNs). This approach enhances matrix processing capabilities, enabling efficient, large-scale computations for complex AI tasks.

Keywords:

matrix vector multiplication photonic computing time-multiplexing

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Last Updated: Jun 5, 2025

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Area of Science:

Neuromorphic photonics
Artificial intelligence hardware

Background:

Photonic circuits offer energy and time efficiency for artificial neural networks (ANNs) due to high bandwidth and low loss.
Scaling current photonic circuits to meet the demands of modern ANNs remains a significant challenge.

Purpose of the Study:

To address the scaling limitations of existing photonic matrix processors for ANNs.
To propose and investigate a novel time-multiplexed matrix processing scheme.

Main Methods:

Overview of matrix sizes in ANNs and comparison with existing photonic matrix processor capabilities.
Proposal and investigation of a time-multiplexed matrix processing scheme using incoherent optical accumulation.
Achieved 98.9% accumulation accuracy with 1 ns pulses.

Main Results:

The proposed scheme virtually increases the size of physical photonic crossbar arrays without electrical post-processing.
Demonstrated high accumulation accuracy (98.9%) for time-multiplexed optical accumulation.
Projected capability for all-optical matrix-vector multiplication of 16,000 × 64 matrices on a 51.2 mm² area.

Conclusions:

The time-multiplexed neuromorphic photonic circuit architecture enables efficient, large-scale matrix operations for ANNs.
This approach facilitates over 110 trillion multiply-accumulate operations per second, overcoming current scaling challenges.