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Published on: March 10, 2011
Setpoint weighted PI-FOPD cascade controllers synthesis for unstable time-delayed processes satisfying prespecified
1Department of Electrical Engineering, Tungnan University, No. 152, Section 3, Peishen Rd., Shenkeng Dist., New Taipei 222, Taiwan.
A novel controller design improves tracking and reduces overshoot for unstable time-delayed processes. This method enhances robustness against disturbances, offering superior performance in simulations and practical applications.
Area of Science:
- Control Engineering
- Process Control
- Automation Systems
Background:
- Unstable time-delayed (UTD) processes present significant control challenges due to inherent instability and delays.
- Existing controllers often struggle to balance rapid tracking, overshoot reduction, and robustness for UTD systems.
- Model order reduction or delay approximation can introduce inaccuracies in controller design for UTD processes.
Purpose of the Study:
- To introduce a novel setpoint weighted PI-FOPD (SWPI-FOPD) cascade controller with a prefilter for UTD processes.
- To develop a four-stage design strategy for enhancing tracking, minimizing overshoot, and ensuring robustness.
- To provide a systematic procedure for controller gain computation applicable to various UTD process orders.
Main Methods:
- A four-stage design strategy involving optimal and robust FOPD (ORFOPD) and PI (ORPI) controllers.
- Utilizing a gain and phase margin (GPM) tester to determine feasible specification-oriented regions (FSORs).
- Implementing setpoint weighting and a prefilter to manage overshoot and refine reference signals.
Main Results:
- The proposed SWPI-FOPD controller demonstrates rapid tracking response with zero steady-state error.
- Significant reduction in overshoot and integral absolute error (IAE) or integral squared error (ISE) is achieved.
- The controller maintains enhanced robustness against ±10% loop gain perturbations (LGPs).
Conclusions:
- The SWPI-FOPD controller with a prefilter offers a robust and effective solution for controlling UTD processes.
- The systematic design procedure facilitates rapid computation of controller gains.
- Validated through simulations and a practical jacketed CSTR application, showcasing superior performance.
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