ITZO-Based Self-Aligned Top Gate Thin-Film Transistor with Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Devices

Background:

• Traditional two-transistor, zero-capacitor (2T0C) memory architectures suffer from parasitic capacitances that limit performance.
• Minimizing these parasitic capacitances is crucial for achieving long data retention and high endurance.

Purpose of the Study:

• To develop a novel 2T0C gain-cell memory with a self-aligned top-gate (SATG) structured thin-film transistor (TFT).
• To engineer an indium tin zinc oxide (ITZO) channel-incorporated architecture that minimizes parasitic capacitance for enhanced memory operations.

Main Methods:

• Fabrication of a 2T0C gain-cell memory utilizing a self-aligned top-gate (SATG) structure.
• Incorporation of an indium tin zinc oxide (ITZO) channel material within the TFT architecture.
• Characterization of memory performance, focusing on retention time, off-current, bias stability, and mobility.

Main Results:

• The SATG design effectively reduced four nonessential parasitic capacitances to near zero, retaining only the essential gate insulator capacitance (C_OX).
• The ITZO-based 2T0C memory demonstrated a retention time exceeding 10,000 seconds.
• Achieved an extremely low off-current (2.33 × 10^-18 A/μm), superior positive-bias stability (0.71 V), and high saturation mobility (17.52 cm²/(V s)).

Conclusions:

• The developed ITZO-based 2T0C gain-cell memory offers a promising solution for next-generation 3D-integrated stacked dynamic random-access memories (DRAMs).
• The novel SATG structure sets a new standard for future memory architectures, emphasizing long retention and high endurance.