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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

668
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
668
MOS Capacitor01:25

MOS Capacitor

666
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
666

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A capacitorless, AC-coupled, monolithic input-stage optimized for multi-channel surface EMG acquisition.

Simos Koutsoftidis, Yacine Belgaid, Guang Yang

    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual International Conference
    |March 5, 2025
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    Summary

    A new input stage for surface electromyography (sEMG) was developed using CMOS technology, enabling smaller, wearable sEMG devices for research and clinical use.

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    Area of Science:

    • Biomedical Engineering
    • Integrated Circuit Design

    Background:

    • Multi-channel surface electromyography (sEMG) systems are crucial for neuromuscular analysis.
    • Current sEMG research setups are often large and desktop-based, limiting portability.

    Purpose of the Study:

    • To design and realize a miniaturized input stage for multi-channel sEMG applications.
    • To optimize the input stage for reduced chip area and improved performance.

    Main Methods:

    • Utilized 0.35 μm CMOS technology for circuit design.
    • Incorporated MOS-based pseudo-resistors and MOS-capacitors for AC-coupling to minimize area.
    • Fabricated and tested 20 channels across five dies.

    Main Results:

    • Successfully designed and realized an optimized input stage for sEMG.
    • Demonstrated performance and variability across fabricated channels.
    • Confirmed biological measurements using commercial electrodes.

    Conclusions:

    • The proposed input stage effectively reduces the size of sEMG systems.
    • This technology can facilitate the development of wearable sEMG products from existing research setups.