The Effect of BEOL Design Factors on the Thermal Reliability of Flip-Chip Chip-Scale Packaging

With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay. However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination of interlayer dielectric (ILD) layers. In order to improve package reliability, the effect of CPI at multi-scale needs to be explored in terms of package integration. In this paper, the stress of BEOL in the flip-chip chip-scale packaging (FCCSP) model during thermal cycling is investigated by using the finite-element-based sub-model approach. A three-dimensional (3D) multi-level finite element model is established based on the FCCSP. The wiring layers were treated by the equivalent homogenization method to ensure high prediction accuracy. The stress distribution of the BEOL around the critical bump was analyzed. The cracking risk of the interface layer of the BEOL was assessed by pre-cracking at a dangerous location. In addition, the effects of the epoxy molding compound (EMC) thickness, polyimide (PI) opening, and coefficient of thermal expansion (CTE) of the underfill on cracking were investigated. The simulation results show that the first principal stress of BEOL is higher at high-temperature moments than at low-temperature moments, and mainly concentrated near the PI opening. Compared with the oxide layer, the low-k layer has a higher risk of cracking. A smaller EMC thickness, lower CTE of the underfill, and larger PI opening help to reduce the risk of cracking in the BEOL.