Scalable Van Der Waals Integration of III-N Devices Over 2D Materials for CMOS-Compatible Architectures

Area of Science:

• Semiconductor technology
• Materials science
• Nanotechnology

Background:

• Moore's Law limitations in silicon transistor scaling.
• Emerging non-group IV materials for heterogeneous integration.
• Need for advanced integration techniques beyond CMOS.

Purpose of the Study:

• Develop scalable van der Waals (vdW) integration technology.
• Integrate III-N devices, 2D materials (graphene, MoS2), and CMOS using back-end-of-line processes.
• Demonstrate beyond CMOS scaling through novel integration methods.

Main Methods:

• Utilized fluidic-assisted self-alignment transfer (FAST) for precise integration.
• Employed vertical 3D and lateral 2D integration strategies.
• Verified vdW interface fidelity through yield, uniformity, and reliability analysis.

Main Results:

• Achieved process accuracy of ≈ 32.6 nm on a 200 mm wafer scale.
• Successfully integrated freestanding III-N chips onto 2D materials.
• Demonstrated multi-layer graphene as a functional back-gating interconnect line.
• Integrated GaN-based radio-frequency power and cascode GaN/Si transistors on SOI-CMOS.

Conclusions:

• The proposed vdW integration approach surpasses physical scaling limits.
• Facilitates functional diversification in semiconductor devices.
• Advances the
• More than Moore
• paradigm through scalable, high-fidelity integration.