Comparison metrics and power trade-offs for BCI motor decoding circuit design

Brain signal decoders are increasingly being used in early clinical trials for rehabilitation and assistive applications such as motor control and speech decoding. As many Brain-Computer Interfaces (BCIs) need to be deployed in battery-powered or implantable devices, signal decoding must be performed using low-power circuits. This paper reviews existing hardware systems for BCIs, with a focus on motor decoding, to better understand the factors influencing the power and algorithmic performance of such systems. We propose metrics to compare the energy efficiency of a broad range of on-chip decoding systems covering Electroencephalography (EEG), Electrocorticography (ECoG), and Microelectrode Array (MEA) signals. Our analysis shows that achieving a given classification rate requires an Input Data Rate (IDR) that can be empirically estimated, a finding that is helpful for sizing new BCI systems. Counter-intuitively, our findings show a negative correlation between the power consumption per channel (PpC) and the Information Transfer Rate (ITR). This suggests that increasing the number of channels can simultaneously reduce the PpC through hardware sharing and increase the ITR by providing new input data. In fact, for EEG and ECoG decoding circuits, the power consumption is dominated by the complexity of signal processing. To better understand how to minimize this power consumption, we review the optimizations used in state-of-the-art decoding circuits.