Improved Hysteresis of High-Performance p-Type WSe₂ Transistors with Native Oxide WO Interfacial Layer

Atomically thin two-dimensional (2D) semiconductors like transition metal dichalcogenides (TMDs) show great promise as new channel materials for next-generation electronic devices. However, their practical implementation is hampered by the lack of suitable gate dielectrics and interfaces that minimize interface and oxide traps. Here, we introduce a novel strategy to improve the dielectric interface of tungsten diselenide (WSe₂) p-type field-effect transistors (p-FETs) by integrating a native oxide, tungsten oxide (WO), as an interlayer into a high-κ hafnium dioxide (HfO₂) back gate stack. The WO interlayer serves as both a doping layer to adjust the threshold voltage (V_TH) and an interfacial layer to improve the WSe₂-HfO₂ interface. The subthreshold swing (SS) in long-channel p-FETs with this gate stack can achieve a near-ideal value (∼68 mV/dec), and hysteresis improves significantly within a 6 V gate sweep range. This work establishes a pathway for high-κ dielectric integration in high-performance 2D electronics.