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Hardware IP protection by exploiting IP vendor's proteogenomic BioMarker as digital watermark during behavioral
Anirban Sengupta1, Nabendu Bhui2, Vishal Chourasia2
1Department of Computer Science and Engineering, Indian Institute of Technology, Indore, 453552, India. asengupt@iiti.ac.in.
Scientific Reports
|April 13, 2025
Summary
This study introduces a novel hardware intellectual property (IP) protection method using proteogenomic bio-markers as digital watermarks (BioW-IPP) to combat IP piracy and ownership claims in system-on-chip (SoC) designs.
Area of Science:
- Computer Engineering
- Digital Hardware Design
- Intellectual Property Protection
Background:
- Intellectual property (IP) piracy and false ownership claims pose significant threats to system-on-chip (SoC) designs and IP vendors.
- The digital hardware design community faces increasing concerns regarding IP design piracy.
- Existing protection methods may lack robust security against sophisticated piracy techniques.
Purpose of the Study:
- To present a novel behavioral synthesis-based hardware IP protection methodology.
- To develop a system for detecting IP piracy and refuting false ownership claims.
- To leverage proteogenomic bio-markers as a unique identifier for IP authentication.
Main Methods:
- Exploiting the IP vendor's proteogenomic bio-marker as a digital watermark (BioW-IPP).
- Generating a robust hardware watermark using the bio-watermark as secret digital evidence (BW-ID).
- Embedding the watermark during the behavioral synthesis/high-level synthesis (HLS) register allocation phase, ensuring minimal design overhead.
Main Results:
- The proposed BioW-IPP approach offers enhanced security against IP piracy and false ownership claims.
- Achieved lower probability of coincidence (watermark collision) compared to prior methods.
- Demonstrated higher tamper tolerance with nominal design overhead.
Conclusions:
- The proteogenomic signature bio-watermark provides a secure and efficient solution for hardware IP protection.
- The method effectively safeguards IP vendor rights and enhances SoC design reliability.
- This approach represents a significant advancement in combating digital hardware piracy.

