2D Materials in Logic Technology: Power Efficiency and Scalability in 2DM-MBC CFET.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Digital evolution necessitates high-performance logic technology with high density, speed, and low power consumption.
• Power consumption is a critical challenge in miniaturized logic devices, affecting reliability and scalability.

Purpose of the Study:

• To review key parameters in logic field-effect transistors (FETs) for managing power consumption.
• To examine advancements in unit and array structures of logic FETs.
• To explore the potential of 2D materials (2DMs) in 3D-stacked structures for ultralow power devices.

Main Methods:

• Review of logic FET development history, structural innovations, and power consumption challenges.
• Investigation of 2D materials (2DMs) in 3D-stacked complementary field-effect transistors (CFETs).
• Analysis of current progress and challenges in 2DM NMOS and PMOS for CFET industrialization.

Main Results:

• Logic FETs require careful parameter management for efficient power consumption.
• 2D materials (2DMs) offer significant benefits for ultralow power consumption in 3D-stacked structures like 2DM-MBC CFETs.
• Development of 2DM NMOS and PMOS for CFET industrialization faces ongoing challenges.

Conclusions:

• Advancements in logic FET structures are crucial for meeting digital evolution demands.
• 2DM-based 3D-stacked CFETs, particularly 2DM-MBC CFETs, represent a promising avenue for future ultralow power logic technology.
• Further research and development are needed to overcome challenges in 2DM CFET industrialization.