A CMOS coarse-fine binary-weighted digital-to-time converter based on size-ratioed pulse expansion

This paper presents a coarse-fine binary-weighted digital-to-time converter (BWDTC) based on a unified timing-generation principle governing both the coarse and fine stages. The fine stage employs a size-ratioed pulse-expanding scheme that achieves finer-than-unit-capacitor resolution through geometric scaling of metal-oxide-semiconductor (MOS) capacitors, while the coarse stage utilizes discrete MOS-capacitor loading, together forming a 2-bit coarse and 3-bit fine partition. This homogeneous coarse-fine structure substantially alleviates the inter-stage calibration burden commonly encountered in conventional heterogeneous implementations. Fabricated in a Taiwan Semiconductor Manufacturing Company 0.35-μm complementary metal-oxide-semiconductor process, the proposed 5-bit BWDTC occupies a core area of 0.098 mm2, achieves a 20-ps fine-stage resolution, and consumes 396 μW at 1 MHz. The measured worst-case integral nonlinearity (INL) is -1.5/+1.8 LSB, while the INL within each operating subrange remains within ±1 LSB. These quantitative results demonstrate the feasibility of homogeneous coarse-fine pulse-expanding integration for compact time-domain digital-to-time conversion.