Low-Power and High-Performance Double-Node-Upset-Tolerant Latch Using Input-Splitting C-Element.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Nanotechnology

Background:

• Data accuracy is crucial for sensor systems.
• Nanoscale CMOS latches are vulnerable to single-node upsets (SNUs) and double-node upsets (DNUs), causing data errors.
• Existing hardened latches often present trade-offs in area, power, or delay.

Purpose of the Study:

• To propose a highly robust Double-Node-Upset-Tolerant Latch-Based on Input Splitting C-Elements (DNUISC).
• To design a latch that mitigates data errors caused by SNUs and DNUs in nanoscale CMOS circuits.
• To improve reliability and reduce power consumption and delay in sensor system components.

Main Methods:

• Designed the DNUISC latch by interconnecting three sets of input-splitting C-elements in a feedback loop.
• Incorporated clock gating and fast-path techniques for power and delay optimization.
• Conducted simulations using the 28 nm process in HSPICE.

Main Results:

• The DNUISC latch demonstrated self-recovery from any single-node upset.
• The DNUISC latch exhibited tolerance to any double-node upset.
• Achieved a 55.21% reduction in area-power-delay product (APDP) compared to existing hardened latches.
• Showcased high reliability and low sensitivity across varying process, voltage, and temperature (PVT) conditions.

Conclusions:

• The proposed DNUISC latch offers significant improvements in robustness and efficiency for sensor systems.
• The design effectively addresses the critical issue of data errors caused by node upsets in nanoscale CMOS latches.
• The DNUISC presents a promising solution for enhancing the reliability of digital circuits in demanding environments.