Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive...

Area of Science:

• Electrical Engineering
• Materials Science
• Computer Engineering

Background:

• Fractional-order elements (FOEs) offer unique impedance characteristics not achievable with traditional integer-order components.
• Implementing FOEs using standard integrated circuit technology has been a significant challenge.
• Existing methods for synthesizing FOEs are often complex and not readily compatible with current manufacturing processes.

Purpose of the Study:

• To present a novel synthesis method for designing fractional-order elements (FOEs) using Metal-Oxide-Semiconductor (MOS) transistors.
• To enable the fabrication of FOEs using existing integrated circuit manufacturing technologies.
• To validate the proposed design approach through simulations.

Main Methods:

• MOS transistors were modeled as uniform distributed resistive-capacitive layer structures.
• A genetic algorithm was employed to optimize MOS transistor interconnections and dimensions for desired FOE characteristics.
• A graphical user interface (GUI) was developed to facilitate the synthesis process.
• The design was validated using Cadence post-layout simulations in TSMC 65 nm technology.

Main Results:

• Successfully synthesized FOEs with admittance phase ranging from 5 to 85 degrees.
• Post-layout simulations confirmed the design's accuracy, showing magnitude and phase errors below 0.5% and 0.1 degrees, respectively.
• The validated frequency range for the synthesized FOEs was from 1 kHz to 10 MHz.

Conclusions:

• The proposed synthesis method effectively designs fractional-order elements (FOEs) using MOS transistors.
• The approach is compatible with current integrated circuit manufacturing technologies, paving the way for practical FOE fabrication.
• The validated simulation results demonstrate high accuracy and suitability for future real-world applications.