Investigating Floating-Gate Topology Influence on van der Waals Memory Performance

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Flash memory scaling faces limitations with silicon-based technologies.
• Van der Waals materials offer a promising alternative for future memory devices.
• Understanding low-dimensional scaling mechanisms is crucial for optimization.

Purpose of the Study:

• To investigate the impact of floating-gate length on memory device characteristics.
• To reveal electrostatic coupling behaviors in low-dimensional memory devices.
• To provide insights for developing next-generation memory technologies.

Main Methods:

• Experimental fabrication of memory devices with varied floating-gate and tunneling-layer configurations.
• Utilizing Technology Computer-Aided Design (TCAD) simulations.
• Characterization of memory window, retention, and endurance.

Main Results:

• Floating-gate length was experimentally shown to significantly affect memory window characteristics.
• A large memory ratio of 82.25% was achieved.
• Good retention (>50,000 s, 8 states) and endurance (>2000 cycles) were demonstrated.

Conclusions:

• Floating-gate topology plays a critical role in manipulating low-dimensional memory devices.
• The findings offer valuable insights for advancing next-generation memory technologies.
• Optimized structural design is key for high-performance, low-dimensional memory.