InAs nanowire transistor pairs as NMOS inverters.

Area of Science:

• Semiconductor Nanowire Technology
• Nanoelectronics
• III-V Materials

Background:

• III-V semiconductor nanowires offer potential for advanced compact and flexible electronic devices.
• Low-power applications require efficient and reliable logic circuits.

Purpose of the Study:

• To integrate pairs of indium arsenide (InAs) nanowires into an inverter configuration for NMOS logic circuits.
• To control transistor threshold voltage by manipulating nanowire diameter and channel length.
• To optimize inverter performance for practical logic applications.

Main Methods:

• Fabrication of InAs nanowire pairs for inverter circuits.
• Control of nanowire diameter (<50 nm for enhancement mode, larger for depletion mode) and channel length.
• Optimization of inverter voltage transfer characteristics via gate and channel geometries and gate dielectric thickness reduction.

Main Results:

• Demonstrated control over threshold voltage by adjusting nanowire dimensions.
• Achieved a full rail-to-rail output voltage swing and a switching ratio of 99.3%.
• Obtained a gain value of 42% and noise margins satisfying cascaded logic circuit requirements.

Conclusions:

• InAs nanowire inverters are viable for NMOS logic applications.
• Device geometry and dimensions are critical for controlling inverter characteristics and performance.
• Optimized nanowire inverters meet essential criteria for integration into larger logic systems.