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Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

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The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
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Field Effect Transistor01:29

Field Effect Transistor

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Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
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The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
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MOSFET: Enhancement Mode01:22

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Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
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MOS Capacitor01:25

MOS Capacitor

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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...
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Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
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All-Inorganic Metal Oxide-Based p-n Heterojunction Ternary-State Transistors.

Minho Jin1,2, Jong Chan Shin3, Jiho Lee3

  • 1Program in Nano Science and Technology, Graduate School of Convergence Science and Technology, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul 08826, Republic of Korea.

ACS Nano
|June 10, 2025
PubMed
Summary
This summary is machine-generated.

This study introduces all-inorganic oxide ternary-state transistors (TSTs) using indium gallium zinc oxide (IGZO) and tellurium selenium oxide (TeSeO). These transistors enable efficient ternary logic, overcoming limitations of current complementary metal-oxide-semiconductor (CMOS) technology.

Keywords:
metal oxidesp-n heterojunction transistorstellurium selenium oxideternary logicternary-state transistors

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Area of Science:

  • Materials Science
  • Electronics Engineering
  • Semiconductor Physics

Background:

  • Current complementary metal-oxide-semiconductor (CMOS) technology faces integration density and energy efficiency limitations.
  • Ternary logic offers a potential solution but is hindered by challenges with existing p-n heterojunction ternary-state transistors (TSTs), particularly those based on organic or 2D materials.
  • Research into all-inorganic oxide-based TSTs has been limited due to the scarcity of suitable p-type oxide semiconductors.

Purpose of the Study:

  • To demonstrate n-type TSTs using an all-inorganic oxide p-n heterojunction channel compatible with CMOS technology.
  • To investigate the switching characteristics and underlying mechanisms of these novel oxide-based TSTs.
  • To validate the practical application of these TSTs in all-inorganic oxide-based ternary logic circuits.

Main Methods:

  • Fabrication of n-type TSTs by forming a p-n heterojunction between n-type indium gallium zinc oxide (IGZO) and p-type tellurium selenium oxide (TeSeO).
  • Characterization of transistor switching behavior, focusing on gate bias-dependent resistance differences and negative differential transconductance.
  • Demonstration of ternary logic functions using the developed IGZO/TeSeO TSTs and p-type TeSeO transistors.

Main Results:

  • Successful demonstration of n-type TSTs with ternary-state switching characteristics using an all-inorganic oxide heterojunction.
  • Observation of negative differential transconductance attributed to resistance variations between IGZO and TeSeO layers.
  • The heterojunction channel structure was found to significantly influence the switching behavior.
  • Practical implementation of all-inorganic oxide-based ternary logic applications was validated.

Conclusions:

  • The developed IGZO/TeSeO heterojunction TSTs offer a promising pathway for advancing ternary logic beyond the limitations of current CMOS technology.
  • These all-inorganic oxide transistors are compatible with CMOS fabrication requirements, including large-area processing and low annealing temperatures.
  • The study highlights the potential of oxide semiconductors for next-generation, energy-efficient electronic devices.