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Published on: March 19, 2016
A High Dynamic Range and Fast Response Logarithmic Amplifier Employing Slope-Adjustment and Power-Down Mode
Yanhu Wang1, Rui Teng1, Yuanjie Zhou2
1Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China.
None:
Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17-30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz-4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode.
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