On-chip mode multiplexing communication based on pixelated superstructure duty cycle optimization

Mode multiplexing, which transmits parallel data information via orthogonal light field modes, has attracted extensive research attention in on-chip high-capacity optical communication. To reduce the device footprint, a mode multiplexer with sub-wavelength pixelated superstructures is proposed. However, due to the accumulation of device fabrication deviation, the communication performance of mode multiplexer will be deteriorated. Herein, we propose a pixelated superstructure duty cycle optimization strategy to decrease the number of cylindrical air holes, which can mitigate the cumulative disturbance of fabrication deviation. The duty cycle of pixelated superstructure is adjusted by eliminating pixels below the specified Figure of Merit threshold, achieving an improvement from 20.6% to 13.9%. Based on this, we optimize a three-mode multiplexer (TE0, TE1, TE2) and demonstrate a mode multiplexing communication by transmitting 72 Gbit/s QPSK-OFDM signals. The experimental results show that the insertion loss of the fabricated three-mode multiplexer reduces by approximately 1.9 dB ∼ 2.8 dB compared with the direct binary search scheme, and the communication sensitivity is optimized about 1.5 dB at the center wavelength of 1550 nm. Our proposed pixelated superstructure duty cycle optimization strategy performs the pixel updating or random mutation by means of roulette method, increasing the randomness of value search during algorithm execution, which will prevent the target value from falling into a local optimal solution. This work is expected to promote the development of on-chip mode multiplexing and provide what we believe to be new technological paths for high-capacity optical communications.