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Related Concept Videos

Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

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In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
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MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

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Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
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MOSFET: Depletion Mode01:20

MOSFET: Depletion Mode

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Depletion-mode MOSFETs represent a unique subset of MOSFET technology, functioning fundamentally differently from their enhancement-mode counterparts. Unlike enhancement MOSFETs, which require a positive gate-source voltage (Vgs) to turn on, depletion-mode MOSFETs are inherently conductive and "normally on" devices.
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity...
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On-chip mode multiplexing communication based on pixelated superstructure duty cycle optimization.

Chaofeng Wang, Houwen Liu, Xue Long

    Optics Express
    |August 13, 2025
    PubMed
    Summary
    This summary is machine-generated.

    This study introduces an optimized pixelated superstructure for mode multiplexers, enhancing on-chip optical communication performance. The new method reduces fabrication errors, improving data transmission efficiency and lowering insertion loss.

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    Area of Science:

    • Photonics and Optical Communications
    • Nanotechnology and Metamaterials

    Background:

    • On-chip optical communication demands high-capacity solutions like mode multiplexing.
    • Sub-wavelength pixelated superstructures offer compact mode multiplexers but suffer from fabrication deviations.
    • Fabrication errors degrade the performance of mode multiplexers in optical communication systems.

    Purpose of the Study:

    • To develop a pixelated superstructure duty cycle optimization strategy for mode multiplexers.
    • To mitigate the impact of fabrication deviations on device performance.
    • To enhance the capacity and efficiency of on-chip optical communication.

    Main Methods:

    • Proposed a duty cycle optimization strategy by eliminating pixels below a Figure of Merit threshold.
    • Reduced the number of cylindrical air holes in the pixelated superstructure.
    • Employed a roulette method for pixel updating and random mutation to avoid local optima.

    Main Results:

    • Achieved a duty cycle improvement from 20.6% to 13.9%.
    • Demonstrated a three-mode multiplexer (TE0, TE1, TE2) transmitting 72 Gbit/s QPSK-OFDM signals.
    • Reduced insertion loss by 1.9–2.8 dB and optimized communication sensitivity by 1.5 dB at 1550 nm compared to direct binary search.

    Conclusions:

    • The proposed optimization strategy effectively reduces fabrication deviation impact on mode multiplexers.
    • This approach enhances performance metrics like insertion loss and communication sensitivity.
    • The work provides a new technological path for high-capacity on-chip optical communications.