Arrayable TDC with Voltage-Controlled Ring Oscillator for dToF Image Sensors.

Area of Science:

• Electrical Engineering
• Integrated Circuit Design
• Metrology

Background:

• Improving time-to-digital converter (TDC) resolution and speed often increases bit error rates, degrading linearity and measurement accuracy.
• Existing TDC designs face challenges with sampling errors and fixed delays affecting precision.

Purpose of the Study:

• To develop a high-linearity, low-power, wide dynamic range TDC.
• To address limitations in current TDC linearity and accuracy for demanding applications.

Main Methods:

• Utilized the SMIC 180 nm BCD process for chip fabrication.
• Implemented a novel phase arbiter structure to eliminate sampling errors.
• Incorporated a preprocessing circuit to mitigate START/STOP signal transmission delay errors.

Main Results:

• Achieved high linearity with Differential Nonlinearity (DNL) between -0.98 LSB and 0.93 LSB, and Integral Nonlinearity (INL) between -0.88 LSB and 0.95 LSB.
• Demonstrated a highest resolution of 156 ps and a maximum measurement time range of 1.2 μs.
• Reported low power consumption of 1.625 mW.

Conclusions:

• The proposed TDC architecture significantly improves linearity and reduces measurement errors compared to previous methods.
• The TDC's simplicity and performance make it suitable for direct time-of-flight (dToF) LIDAR, enabling accurate distance measurements up to hundreds of meters with 2.25 cm accuracy.
• The design achieves high accuracy without requiring post-processing or time calibration.