Scalable Inter-Dielectric Engineering via Vapor-Phase Synthesis Process for Top-Gate MoS₂ Thin-Film Transistor

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Two-dimensional (2D) semiconductors are key for next-generation thin-film transistors (TFTs) in Internet of Things (IoT) devices.
• Integrating high-k dielectrics with 2D materials like MoS2 is challenging due to inert surfaces, leading to interface defects and performance issues.

Purpose of the Study:

• To develop a scalable strategy for uniform high-k dielectric integration on 2D semiconductors.
• To improve the interface quality and electrical characteristics of MoS2-based transistors.

Main Methods:

• Utilized initiated chemical vapor deposition (iCVD) to deposit an ultrathin poly(1,3,5-trimethyl-1,3,5-trivinylcyclotrisiloxane) (pV3D3) interlayer between MoS2 and HfO2.
• Engineered an overlapping top-gate structure to minimize contact resistance.

Main Results:

• The pV3D3 buffer layer uniformly formed on MoS2, preventing pinholes and clusters.
• Achieved suppressed HfO2-induced doping and trap formation, resulting in transistors with near-ideal switching (SS of 60.9 mV/dec), low hysteresis (≈20 mV), and low interface trap density (8.9 × 10^10 cm^-2 eV^-1).
• Demonstrated high performance with an I_ON/I_OFF ratio > 10^8, field-effect mobility (µ_FE) of 19.2 cm^2 V^-1 s^-1, and SS_min of 80.6 mV/dec^-1.

Conclusions:

• The iCVD-based inter-dielectric engineering is a scalable and effective method for high-performance 2D electronics.
• Validated the approach on flexible MoS2 transistors and logic circuits, showing potential for large-area applications.