Low-Voltage Driven High-Speed and Low-Energy Memory Operations by Novel TiTe₂/Sc_0.3Sb₂Te₃ Phase-Change...

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Phase-change memory (PCM) faces challenges like slow Set speeds, high Reset energy, and multilevel resistance drift.
• These drawbacks hinder the development of high-capacity storage and high-parallel computing chips, especially for nodes below 16-40 nm requiring low driving bias.

Purpose of the Study:

• To design and investigate an innovative TiTe2/Sc0.3Sb2Te3 heterostructure to overcome PCM performance limitations.
• To achieve simultaneously improved Set speed, Reset energy, and multilevel resistance stability under low-voltage conditions.

Main Methods:

• Fabrication of TiTe2/Sc0.3Sb2Te3 heterostructure-based PCM cells.
• In situ electrical-pulse driven microscopic observation of phase-transition mechanisms.
• Electrical performance characterization, including Set speed, Reset energy, and multilevel resistance drift.

Main Results:

• The heterostructure demonstrated the lowest Reset energy (≈6.40 pJ bit⁻¹).
• Achieved the fastest Set speed (≈4 ns) within the low-voltage regime (< ≈2.5 V), with sub-ns capability (≈0.6 ns) at higher bias.
• Exhibited the smallest multilevel resistance drift (≈10⁻⁴-3 × 10⁻³), outperforming existing cells.

Conclusions:

• The TiTe2/Sc0.3Sb2Te3 heterostructure offers a viable solution for superior PCM performance.
• Understanding the reversible 2D phase-transition mechanisms is key to enhanced electrical properties.
• This work provides guidance for designing novel chalcogenide heterostructures for advanced memory applications.