Efficient spiking convolutional neural networks accelerator with multi-structure compatibility.

Area of Science:

• Neuromorphic Engineering
• Computer Architecture
• Artificial Intelligence

Background:

• Spiking Neural Networks (SNNs) offer superior energy efficiency and biological plausibility compared to traditional neural networks.
• Spiking Convolutional Neural Networks (SCNNs) show great promise for low-power, brain-like computing applications, particularly in object detection.
• Existing hardware accelerators for SCNNs often lack compatibility with complex network architectures.

Purpose of the Study:

• To propose an efficient Field-Programmable Gate Array (FPGA) accelerator architecture for SCNNs.
• To ensure multi-structure compatibility, supporting both convolutional and residual topologies for diverse network scales.
• To enhance computational speed and energy efficiency for SCNN hardware acceleration.

Main Methods:

• Developed a clock-driven FPGA architecture for convolution and neuron updates using spike-encoded data.
• Implemented hierarchical pipelining and channel parallelization to boost SCNN computation speed.
• Integrated configuration and scheduling methods (grouped reuse computation, line-by-line multi-timestep computation) to accelerate deep networks.

Main Results:

• The accelerator achieved 1,605 frames/s for a small-scale LeNet network with 0.65 mJ/image energy consumption.
• For a deep residual SCNN, the accelerator provided 2.59x the processing speed of a CPU.
• The deep residual SCNN processing consumed only 16.77% of the CPU's power.

Conclusions:

• The proposed FPGA accelerator architecture demonstrates high energy efficiency, compatibility, and applicability for SCNNs.
• The design effectively accelerates both simple and complex SCNNs, including deep residual networks.
• This work advances hardware acceleration for SNNs, enabling more efficient brain-like computing systems.