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p-GaN source integrated GaN/AlGaN/GaN double heterojunction field-effect transistor (FET) for next-generation
Mohit Kumar1, Timothée Labau2,3, Laurent Xu2
1Univ. Grenoble Alpes, CEA, Leti, Grenoble, 38000, France. mohit.kumar@cea.fr.
Scientific Reports
|October 21, 2025
Summary
This study optimizes Gallium Nitride (GaN) p-field-effect transistors (p-FETs) using a dual-channel design for enhanced performance. Optimized GaN p-FETs achieve superior control, high on/off ratios, and reduced leakage for advanced electronics.
Area of Science:
- Semiconductor Physics
- Materials Science
- Device Engineering
Background:
- High-power and high-frequency electronics require advanced semiconductor materials.
- Gallium Nitride (GaN) field-effect transistors (FETs) offer superior performance characteristics.
- Existing GaN FETs face challenges in achieving optimal carrier confinement and mobility.
Purpose of the Study:
- To investigate and optimize a novel GaN p-FET device architecture.
- To explore the impact of key design parameters on device performance.
- To achieve high-performance and reliable GaN-based electronics.
Main Methods:
- Device simulation of n-GaN/AlGaN/GaN double heterostructure FETs with a p-GaN source.
- Systematic examination of Mg2+ doping, contact metal work function, AlGaN thickness, and Al mole fraction.
- Analysis of two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) channel formation.
Main Results:
- An optimized GaN p-FET with a 5 nm p-GaN layer (1×1019 cm-3 Mg2+) and a 10 nm AlGaN layer (0.2 Al mole fraction) demonstrated superior performance.
- Achieved optimal threshold voltage control (~|4| V), high ION/IOFF ratios (0.39×1012), and minimized leakage current.
- A contact metal work function of 5.15 eV significantly reduced contact resistivity and leakage current.
Conclusions:
- The proposed dual-channel GaN p-FET architecture significantly enhances carrier confinement and mobility.
- Precise control over doping, layer thickness, and composition is crucial for optimizing GaN p-FET performance.
- This optimized device configuration is essential for next-generation high-performance and reliable electronic applications.
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