Enhancing Gate Control and Mitigating Short Channel Effects in 20-50 nm Channel Length Amorphous Oxide Thin-Film...

Area of Science:

• Semiconductor Device Physics
• Materials Science
• Nanotechnology

Background:

• Single-gate field-effect transistors (FETs) face challenges with short channel effects like drain-induced barrier lowering (DIBL) as channel lengths decrease.
• Advanced geometries like dual-gate or gate-all-around improve gate control but increase fabrication complexity.

Purpose of the Study:

• To investigate the reduction of short channel effects in single-gate FETs using a novel nanospike electrode design.
• To demonstrate comparable performance metrics to larger conventional FETs through improved gate control.

Main Methods:

• Fabrication of single-gate FETs using indium gallium zinc oxide channels and nanospike source/drain electrodes.
• Utilized a 9 nm Al2O3 gate insulator and independent Ni gates in a bottom-gate configuration.
• Employed Synopsys Sentaurus simulations to analyze device physics and performance.

Main Results:

• Nanospike electrodes significantly reduce short channel effects in FETs with 20-25 nm channel lengths.
• Achieved DIBL and other key metrics comparable to conventional FETs with 70-80 nm channel lengths.
• Attributed improvements to enhanced gate control near the nanospike electrode tips.

Conclusions:

• The nanospike electrode design offers a viable solution to mitigate short channel effects in single-gate FETs.
• This approach simplifies fabrication while achieving high performance, beneficial for back-end-of-line semiconductor technologies.