A Reconfigurable Silicon Transistor for Noise-Resilient Stochastic Spiking Neural Networks

Spiking neural networks (SNNs) are energy-efficient neuromorphic architectures that emulate the event-driven signaling of biological neurons. However, their reliance on deterministic neuron models limits their ability to capture the intrinsic stochasticity of real neural systems, limiting their noise resilience and adaptability. To overcome these limitations, stochastic SNNs (SSNNs) have emerged, incorporating probabilistic behavior to enhance noise tolerance and enable probabilistic exploration. In this study, we implemented a neuronal transistor (neuristor) by reengineering conventional CMOS technology based on well-established silicon and its derivatives, enabling dual functionality by exhibiting both stochastic and deterministic properties for reliable and noise-resilient SSNNs. The neuristor integrates stochastic encoding in the input layer and leaky integrate-and-fire (LIF) behavior in the hidden and output layers within a single device. The neuristor utilizes the single transistor latch (STL) mechanism, where impact ionization induces stochastic spiking under specific conditions, while controlled charge accumulation triggers LIF firing under others. This reconfigurable dual-mode operation enables the same neuristor to function across all network layers, simplifying circuit design and enhancing scalability. A neuristor-based SSNN achieved 92% classification accuracy on the MNIST data set under 30% Gaussian noise, demonstrating strong noise resilience and validating its applicability for biologically inspired, energy-efficient neuromorphic systems.