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Optical Waveguide-Pair Design for CMOS-Compatible Hybrid III-V-on-Silicon Quantum Dot Lasers
Peter Raymond Smith1, Konstantinos Papatryfonos1,2, David R Selviah1
1Department of Electronic and Electrical Engineering, University College London, London WC1E 7JE, UK.
Nanomaterials (Basel, Switzerland)
|November 12, 2025
Summary
Researchers developed a novel hybrid laser design for silicon photonics, improving light coupling in 220-nm silicon waveguides for efficient data communication. This compact, energy-efficient laser is robust for advanced optical interconnects.
Area of Science:
- Silicon Photonics
- Integrated Optics
- Semiconductor Lasers
Background:
- Compact, energy-efficient lasers at 1.3 µm are crucial for data communications and optical interconnects.
- Hybrid III-V-on-silicon lasers offer potential but face challenges in III-V/Si optical coupling, especially with standard 220-nm silicon waveguides.
Purpose of the Study:
- To numerically study distributed Bragg reflector (DBR) hybrid III-V-on-silicon lasers.
- To analyze design trade-offs and optimization strategies for 220-nm-thick silicon waveguides.
- To propose a novel epitaxial design for effective III-V/Si coupling and mode transfer.
Main Methods:
- Numerical simulations based on supermode theory.
- Analysis of mode profiles dependence on silicon waveguide dimensions and III-V stack geometry/composition.
- Investigation of epitaxial design for optimized optical confinement and mode transfer.
Main Results:
- Identified dependencies between mode profiles, silicon waveguide dimensions, and III-V stack characteristics.
- Proposed a novel epitaxial design enabling effective III-V/Si coupling.
- Demonstrated strong optical mode confinement in the III-V gain section and efficient transfer to the silicon waveguide.
Conclusions:
- The proposed novel epitaxial design facilitates effective III-V/Si coupling using 220-nm-thick silicon waveguides.
- The design ensures efficient optical mode transfer between gain and passive sections.
- The developed hybrid laser design exhibits robustness against fabrication variations, crucial for CMOS compatibility.

