CTE match of copper foil and build-up film/core board in FCBGA substrate reduces warpage

The rapid advancement of high-performance computing (HPC) and artificial intelligence (AI) has driven escalating demands for chip performance and integration. As next-generation HPC processors, advanced graphics processing units (GPUs) employ CoWoS-L packaging technology to achieve superior integration and performance. However, substrate warpage in flip-chip ball grid array (FCBGA) packages has emerged as a critical challenge, compromising yield and reliability during packaging processes. In this study, warpage mitigation was investigated by using the Grace T.H.W. Group's proprietary materials, such as laminate substrates, build-up films, glass/quartz fabrics, epoxy resins, and optimized copper foils and fillers. The experimental results demonstrate that these proprietary materials successfully overcome the warpage issue of FCBGA substrates. These materials improve FCBGA reliability, reduce chip failure risk, and ensure overall system safety, particularly for GPU-dependent applications such as autonomous vehicles and AI robotics, for which computational integrity is essential. The correlation between the coefficient of thermal expansion (CTE) for FCBGA substrate materials and warpage behaviour was determined. Experiments confirmed that aligning the XY-CTE of build-up films and core boards with copper foils (18 ppm/°C), rather than conventional chip-centric matching (5 ppm/°C), reduced FCBGA substrate warpage by 92%. This approach markedly improved the reliability of large-scale integrated chips (LSIs), such as in ASICs, CPUs, and high-end GPUs.