Dynamic-Depleted Transistor Empowering Logic-in-Coding Computing.

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• Conventional reconfigurable transistors have limitations in logic function complexity and efficiency.
• Existing designs often require additional circuits, leading to redundancy and increased power usage.

Purpose of the Study:

• To introduce a dynamic-depletion transistor architecture for enhanced reconfigurable logic circuits (RLCs).
• To achieve multiple logic functions within a single device through electrostatic modulation.

Main Methods:

• Developed a dynamic-depletion transistor architecture using electrostatic modulation of carrier depletion profiles.
• Utilized a 2D WSe2 transistor to precisely control carrier distribution via a control gate.
• Demonstrated transitions between fully depleted and partially depleted states within the same device.

Main Results:

• The proposed architecture integrates up to five reconfigurable logic functions.
• Circuits achieved standard digital functions with significantly reduced transistor counts (40% and 25% of CMOS).
• Successfully implemented reconfigurable digital image processing tasks, showcasing low-integration, high-computing power.

Conclusions:

• The dynamic-depletion transistor architecture offers a pathway to highly flexible and efficient RLCs.
• This approach minimizes circuit redundancy and power consumption.
• Demonstrated potential for advanced applications like digital image processing with reduced hardware complexity.