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Updated: Jan 9, 2026

Assembly and Characterization of Biomolecular Memristors Consisting of Ion Channel-doped Lipid Membranes
Published on: March 9, 2019
Algorithm-Compatible Single-Transistor Neuron and Al/ZrO2/TiO2/AlOx Memristor Synapse Kernel for Spiking Neural
Yu Lin Zou1, Sunwoo Cheong1, Jea Min Cho1
1Department of Materials Science and Engineering and Inter-University Semiconductor Research Center, College of Engineering, Seoul National University, Seoul 08826, Republic of Korea.
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Memristive neuromorphic computing systems, which combine memory and processing units, are expected to achieve high energy efficiency. However, practical implementations often face challenges due to the complexity of complementary metal-oxide-semiconductor (CMOS) neurons and integration issues related to memristive synapses. In this work, a physical spiking neural network (SNN) system is introduced, featuring two silicon-based one-transistor (1T) neurons and an Al/ZrO2/TiO2/AlOx/Al (AZTA) memristive synapse for on-chip learning. The 1T neuron exhibits a natural latch effect, generating spikes that serve as both an encoder and a decoder. Meanwhile, the AZTA memristor enables analog weight updates through its inherent long-term potentiation and depression plasticity. The combined physical kernel enables algorithm-compatible on-chip learning and inference without the need for complex peripheral circuits, resulting in low energy consumption, high scalability, and dense integration. The compact two-transistor-one-transistor-one-resistor (2T-1T1R) kernel, which learns in real-time using a modified spike-time-dependent plasticity rule, can potentially achieve 91.53% classification accuracy on the MNIST data set, and 75.28% on the challenging Fashion-MNIST data set, in an unsupervised manner if the device uniformity is sufficiently high, as demonstrated through Python simulations. It delivers competitive accuracy compared to the latest CMOS-based SNN processors while significantly reducing energy use (a 1784× decrease per update and a 1350× decrease per inference) with minimal hardware complexity.
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