High Performance Multiple Inversion Layer Selective Buried Triple Gate Vertical Trench Power MOSFET

This paper analyses the various properties that governs a power MOSFET for a novel and unique vertical triple gate selective buried trench power MOSFET. Our recent work consists of a MOSFET having two lateral selective buried gates and a single vertical trench gate facing the drift region, resulting in a Triple gate power MOSFET (TGSBTPMOS). This unique combination of three gates results in significantly high device ON-state current and ultra-low ON resistance of about 0.38 mΩ.cm² in the voltage class of 78.8 V. Our proposed device has multiple inversion layers, which helps in enlarging the channel width and on-current of the device, resulting in better static state and switching performance compared to the conventional power MOSFET. 2-D Silvaco ATLAS simulation output has revealed the outperformance of the proposed device in all the areas governing power MOSFET, i.e., gate-to-drain charge (Qgd), device transfer and output (I-V) characteristic, Balliga's Figure of Merits (FOM1 and FOM2). Furthermore, the proposed device achieves 4.86 orders of magnitude improvement in FOM1, 68.85% in Ron.sp, 94.54% in Qgd, and 98.34% in FOM2. Our proposed device is an enhancement in the existing state of the art and competes with the reported power MOSFET structure in terms of performance.