Area efficient approximate multiplier based on novel 4:2 compressors and error correction logic

Area of Science:

• Computer Engineering
• Digital Circuits
• Approximate Computing

Background:

• Multipliers are crucial for arithmetic circuits, impacting system performance.
• Approximate computing offers energy and speed improvements for applications with tolerance for minor accuracy loss.
• Designing efficient multipliers involves balancing hardware complexity and computational precision.

Purpose of the Study:

• To introduce novel approximate multiplier architectures.
• To enhance energy efficiency, processing speed, and hardware resource utilization.
• To achieve a better trade-off between hardware efficiency and computational accuracy.

Main Methods:

• Partitioning multiplier computation into accurate, approximate, and lower regions.
• Utilizing novel two 4:2 compressors with conventional arithmetic circuits for partial product compression.
• Developing error correction logic to compensate for inaccuracies.
• Evaluating designs using benchmark error metrics and hardware synthesis in 32-nm CMOS technology.
• Conducting real-time image multiplication experiments with SSIM and PSNR evaluation.

Main Results:

• Achieved average improvements: 70.6% in accuracy, 60.4% in Energy-Delay Product, 30.9% in Power-Delay Product, and 41.6% in delay.
• Demonstrated superior performance compared to existing approximate multiplier designs.
• Showcased higher SSIM and PSNR values in image multiplication experiments with reduced error concentrations.

Conclusions:

• The proposed approximate multipliers offer significant improvements in accuracy and performance metrics.
• These novel architectures provide a superior trade-off between hardware efficiency and computational accuracy.
• The designs are suitable for applications requiring high-speed, energy-efficient computation with minimal accuracy loss, as evidenced by image processing results.