Native GaN/GaO_x Heterostructure Platform for Wafer-Scale Integration of High-Performance Complementary Transistors

Area of Science:

• Materials Science
• Semiconductor Physics
• Nanotechnology

Background:

• Silicon scaling limitations necessitate new materials for post-Moore era electronics.
• Dielectric/semiconductor interface engineering is crucial for advanced transistor performance.
• Existing integration methods compromise interface quality and scalability.

Purpose of the Study:

• To develop a novel in-situ oxidation strategy for high-κ dielectric formation.
• To enable high-performance complementary transistors using low-dimensional semiconductors.
• To establish a scalable integration platform for wafer-scale, low-power electronics.

Main Methods:

• In-situ oxidation to form gallium oxide (GaOx) dielectric on n-type gallium nitride (GaN).
• Integration of n-type molybdenum disulfide (MoS2) and p-type carbon nanotube transistors.
• Characterization of GaN/GaOx heterostructure and device performance.

Main Results:

• Achieved ultra-low interface trap density (1.18 × 10^11 cm^-2 eV^-1) in MoS2 transistors.
• Demonstrated subthreshold swing (SS) at the thermionic limit of 60 mV dec^-1.
• Reported high on/off ratio (>10^8) and significant voltage gain (134.5) for complementary inverters.

Conclusions:

• The GaN/GaOx heterostructure provides a native, scalable, and CMOS-compatible integration platform.
• This approach offers a transformative route toward wafer-scale, energy-efficient electronics.
• The developed method addresses key bottlenecks in integrating advanced semiconductor materials.