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FZC-TDE: The Algorithm for Real-Time Ultrasonic Stress Measurement at Low Sampling Rates
Feifei Qiu1, Bing Chen1, Chunlang Luo1
1School of Materials Science and Engineering, Southwest Jiaotong University, Chengdu 610031, China.
Abstract:
Micro-nano-sized processing equipment requires high levels of precision, necessitating residual stress measurement to maintain stability. Ultrasonic stress measurement is an effective method but is hindered by high sampling-rate requirements, leading to excessive power consumption and hardware costs. This study presents a low-sampling-rate method based on the novel Frequency-domain Zero-padded Cross-correlation Time Delay Estimation (FZC-TDE) algorithm. Tensile validation experiments determined the minimum hardware sampling-rate requirement: rates below 25 MSps (even with interpolation) fail to characterize temporal delay variations effectively, and a rate of at least 20 times the signal frequency is required for ±10 MPa accuracy. The proposed FZC-TDE utilizes a frequency-domain fusion operation (frequency-domain zero-padding interpolation combined with cross-correlation) to enable real-time, high-resolution delay measurement at low rates. Comparative experiments show that time-domain interpolation methods (Linear, PCH, Cubic Spline) achieve similar stress estimation accuracy at the same rate (e.g., 7.4-8.7 MPa error at 100 MSps), while FZC-TDE (10.3 MPa error) offers superior computational efficiency. At 100 MSps, FZC-TDE maintains a stable computation time (~2.8 ms), while those of interpolation methods increase significantly (20-30 ms) due to higher oversampling factors. Furthermore, FZC-TDE reduces the number of arithmetic operations by 75% (2.26 million vs. ≥9.18 million for 128× oversampling on 1024 points) and exhibits slower computational load growth with oversampling ratios. Thus, FZC-TDE provides an optimal balance of acceptable accuracy and significantly enhanced efficiency, particularly for real-time or resource-constrained applications. This work reduces sampling-rate constraints and supports advancements in micro-nano-sized processing equipment and device performance.
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