Highly hardware-efficiency implementation for W-band PAM8 signal reception with additive powers-of-two quantization

In this study, we demonstrate a hardware-efficient post-equalization implementation for PAM8 signals on an FPGA platform by utilizing an additive power-of-two (APoT) quantization scheme. This approach reduces hardware resource consumption by over 70% compared to conventional methods while preserving critical performance metrics. In a 300-m W-band wireless communication experiment, the system reliably transmits 22.1184 Gbit/s PAM8 signals and satisfies the 2.4 × 10^-2 soft-decision forward error correction (SD-FEC) standard. Notably, under a host-assisted workflow, the APoT scheme achieves performance equivalent to 16-bit uniform quantization and exhibits superior stability than PoT quantization.