Thermal Expansion-Engineered Ferroelectric Transistor Arrays for Scalable Edge AI Computing

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Von Neumann architectures face energy and latency issues in AI due to separate memory and logic.
• Ferroelectric transistors offer potential for in-memory computing but require reconfigurability.

Purpose of the Study:

• To develop a reconfigurable ferroelectric transistor platform for efficient AI workloads.
• To demonstrate the feasibility of in-memory computing using these novel devices.

Main Methods:

• Engineered metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structures with tungsten (W) or titanium nitride (TiN) gate electrodes.
• Utilized a hafnium zirconate (HZO) ferroelectric layer and evaluated device performance metrics.
• Simulated a VGG-8 convolutional neural network and performed experimental array operations.

Main Results:

• Achieved high performance in W-gated MFMIS-FeFETs: large memory window (~11 V), >10^6 on/off ratio, 10^12 endurance cycles, and 22 programmable states.
• Demonstrated 97.2% accuracy for CIFAR-10 classification in a simulated VGG-8 network under nonidealities.
• Experimentally realized analog-domain convolution for edge detection and feature extraction in FeFET arrays.

Conclusions:

• Reconfigurable MFMIS-FeFET arrays are a scalable, low-power platform for neuromorphic and compute-in-memory systems.
• Monolithic integration of memory and logic is enabled, addressing von Neumann bottlenecks.
• The technology supports intelligent edge systems and future beyond-CMOS computing paradigms.