A Hardware-Friendly Joint Denoising and Demosaicing System Based on Efficient FPGA Implementation

Area of Science:

• Computer Vision
• Hardware Acceleration
• Image Processing

Background:

• Image acquisition often suffers from noise and color filter array artifacts.
• Existing methods for denoising and demosaicing may lack efficiency for real-time hardware implementation.
• Developing integrated solutions is crucial for improving image quality and processing speed.

Purpose of the Study:

• To design a hardware-accelerable system for joint denoising and demosaicing.
• To propose a lightweight neural network architecture for efficient image processing.
• To develop a unified hardware platform for flexible acceleration.

Main Methods:

• A lightweight network architecture utilizing partial convolution and multi-scale feature extraction was developed.
• Separable and partial convolutions were employed to minimize model parameters and computations.
• A configurable hardware acceleration platform was implemented on a Xilinx Zynq UltraScale+ FPGA.

Main Results:

• The proposed method achieved significant reductions in parameters (83.38%) and MACs (77.71%) compared to standard convolutions.
• On the Kodak24 dataset, improvements of 2.36dB in PSNR and 0.0806 in SSIM were observed.
• Computing efficiency was enhanced by 2.09x, with a hardware architecture supporting multi-parallelism.

Conclusions:

• The proposed system offers a hardware-implementable solution for joint denoising and demosaicing with superior performance.
• The lightweight network and efficient hardware platform provide advantages in model complexity and processing speed.
• The adaptable architecture is suitable for various edge-embedded image processing scenarios.