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Architecture Design of a Convolutional Neural Network Accelerator for Heterogeneous Computing Based on a Fused

Yang Zong1, Zhenhao Ma1, Jian Ren1

  • 1School of Information Science and Engineering, Shenyang University of Technology, Shenyang 110870, China.

Sensors (Basel, Switzerland)
|January 28, 2026
PubMed
Summary

This study introduces a novel, low-power Convolutional Neural Network (CNN) accelerator using heterogeneous computing. The design significantly enhances energy efficiency for embedded applications, outperforming existing solutions.

Keywords:
convolutional neural networkhardware acceleratorheterogeneous computingoperator fusionsystolic array

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Hardware Acceleration

Background:

  • Convolutional Neural Networks (CNNs) face challenges with high computational demands, resource usage, and complexity, limiting their deployment on microprocessors.
  • Current CNN accelerators exhibit limited energy efficiency (2.32-6.5925 GOPs/W), failing to meet low-power embedded system requirements.

Purpose of the Study:

  • To propose a low-power, high-energy-efficiency CNN accelerator architecture.
  • To address the deployment limitations of CNNs in resource-constrained embedded scenarios.

Main Methods:

  • Developed a heterogeneous computing architecture combining a Central Processing Unit (CPU) and Application-Specific Integrated Circuit (ASIC).
  • Implemented an operator-fused systolic array algorithm with YOLOv5n as the benchmark network.
  • Integrated a 2D systolic array with Conv-BN fusion for deep operator fusion (convolution, batch normalization, activation).
  • Optimized a RISC-V core for reduced resource utilization and employed a locking mechanism with prefetching for asynchronous platform stability.

Main Results:

  • Achieved a computational performance of 20.6 GFLOPs.
  • Demonstrated a low power consumption of 1.96 W.
  • Attained an energy efficiency ratio of 10.46 GOPs/W.
  • Showcased a 58-350% improvement in energy efficiency compared to existing mainstream accelerators.

Conclusions:

  • The proposed heterogeneous CNN accelerator architecture offers significant improvements in energy efficiency and performance.
  • The design shows strong potential for effective deployment in low-power embedded systems.
  • The operator-fused systolic array and optimized RISC-V core contribute to overcoming CNN deployment challenges.