A broadband mismatch calibration prototype application-specific integrated circuit for time-interleaved...

Various data acquisition systems have been developed based on the time-interleaved analog-to-digital converter (TIADC) technique, in which digital calibration is typically implemented on field-programmable gate arrays (FPGAs). However, FPGA-based TIADC systems suffer from high power consumption, high implementation complexity, limited hardware resources, and low integration efficiency. In this work, we propose a systematic design method to reduce the resource consumption of TIADC systems. By analyzing the characteristics of filter coefficients and optimizing allocation of computational errors, a resource-efficient digital calibration filter is proposed, achieving over 80% reduction in area and power consumption. A multi-phase sampling clock generation circuit with adjustable delay is integrated to simplify system implementation and provide coarse timing mismatch adjustment. Furthermore, the proposed architecture supports calibration of high-speed ADCs with different resolutions. To validate the proposed approach, a prototype application-specific integrated circuit (ASIC) was implemented in a 130 nm CMOS technology. The chip is designed to interface with up to four 5-Gsps ADCs and consumes 11.5 W of power. Simulation and analysis results demonstrate that broadband mismatch errors can be effectively calibrated by the ASIC. According to the scaling model, if fabricated in a process node comparable with that of modern FPGAs, the ASIC would achieve more than 90% reduction in power consumption relative to FPGA-based implementations consuming several tens of watts, while also lowering the implementation complexity of the TIADC system.