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A Fabrication and Measurement Method for a Flexible Ferroelectric Element Based on Van Der Waals Heteroepitaxy
Published on: April 8, 2018
Van der Waals Ferroelectric CuInP2S6-based Multi-slope In-memory Probabilistic Computing
Changyoung Kim1,2, Namju Kim3, Seongkweon Kang1,2
1SKKU Advanced Institute of Nanotechnology (SAINT), Sungkyunkwan University, Suwon, Republic of Korea.
Researchers developed a novel probabilistic bit (p-bit) by integrating stochastic bit generation and memory into a single device using CuInP2S6. This in-memory computing approach significantly enhances efficiency and performance for complex computations.
Area of Science:
- Materials Science
- Computer Engineering
- Quantum Computing
Background:
- Conventional probabilistic computing (p-computing) architectures suffer from a memory bottleneck due to the physical separation of bit generation and storage.
- Probabilistic bits (p-bits) are essential for p-computing, but current designs face limitations in efficiency and integration.
Purpose of the Study:
- To experimentally integrate voltage-tunable stochastic bit generation and non-volatile memory functionalities into a single in-memory device.
- To realize an efficient p-bit using the van der Waals ferroelectric CuInP2S6 (CIPS) material.
- To demonstrate the advantages of in-memory p-computing over conventional architectures.
Main Methods:
- Utilized the stochastic displacement of Cu+ ions and remanent polarization in CIPS under an external electric field.
- Developed an in-memory device combining p-bit generation and non-volatile memory.
- Performed NP-hard simulations to compare in-memory p-computing with conventional p-computing.
Main Results:
- Achieved stable random bit retention (>1000 s) with low power consumption (∼75 nW).
- Demonstrated reduced time-complexity from O(n^2) to O(n^1.5) for NP-hard problems via in-memory p-computing.
- Showcased dynamic tuning of the probabilistic output's sigmoid slope by varying CIPS layer thickness, enabling adaptive control and reducing convergence steps by 400-fold.
Conclusions:
- The CIPS-based in-memory p-bit eliminates data transfer bottlenecks, enabling efficient and high-performance p-computing.
- This integrated device offers a compact, energy-efficient platform for scalable and adaptive p-computing.
- Dynamic sigmoid slope tunability provides adaptive control crucial for optimizing computational tasks.
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