3D-integrated photonic-electronic co-designed 4 × 160 Gb/s low-power high-density silicon photonic receiver with...

Area of Science:

• Photonics and optoelectronics
• Integrated circuit design
• High-speed communication systems

Background:

• Optical interconnects are crucial for modern computing, demanding higher data rates and energy efficiency.
• Existing silicon photonic receivers face limitations in bandwidth, sensitivity, and integration density.
• Advancements in microring resonator (MRR) technology and photonic-electronic co-design offer potential solutions.

Purpose of the Study:

• To develop and demonstrate a 3D-integrated silicon photonic receiver with enhanced performance.
• To leverage MRR filtering and chip-on-board (CoB) flip-chip assembly for improved integration.
• To evaluate the receiver's data rate, sensitivity, bandwidth, and energy efficiency.

Main Methods:

• Utilized a 3D-integrated silicon photonic architecture with MRR filters.
• Employed chip-on-board (CoB) flip-chip assembly for receiver integration.
• Incorporated inductive peaking and equalization for optical-to-electrical (O-E) bandwidth enhancement.
• Tested with 160 Gb/s four-level pulse-amplitude-modulation (PAM-4) signaling.

Main Results:

• Achieved an aggregate data rate of 640 Gb/s across four channels.
• Demonstrated MRRs with a narrow full width at half maximum (FWHM) of ~0.46 nm (~57.5 GHz).
• Reached an O-E 3 dB bandwidth of 43 GHz.
• Obtained receiver sensitivities of -2.25 dBm under the KP4-FEC threshold for 160 Gb/s PAM-4.
• Attained excellent energy efficiency of 0.83 pJ/bit and bandwidth density of 426.7 Gb/s/mm².
• Experimentally confirmed a clean 200 Gb/s eye diagram, showing scalability.

Conclusions:

• The presented 3D-integrated silicon photonic receiver demonstrates state-of-the-art performance.
• The architecture is highly scalable for future optical input/output (I/O) in xPU packages and inter-chip interconnects.
• Potential exists for further optimization to achieve 200 Gb/s per lane.