Micro-LED/van der Waals heterointegration for in-pixel processing display architecture

Area of Science:

• Materials Science
• Computer Engineering
• Electrical Engineering

Background:

• Conventional display architectures face latency and energy challenges.
• In-memory computing integrated at the pixel level offers a solution for co-located processing and display.
• Intelligent display technologies are rapidly advancing edge smart systems.

Purpose of the Study:

• To develop an in-pixel processed display-driven architecture.
• To integrate micro-LEDs with MoS2 in-memory transistors for enhanced display functionality.
• To demonstrate in-situ image reconstruction and real-time display with reduced latency and energy consumption.

Main Methods:

• Fabrication of a 16x16 active display array with integrated micro-LEDs and MoS2 in-memory transistors.
• Characterization of pixel performance, including luminance, speed, and dimensions.
• Demonstration of in-situ image reconstruction and neural network inference directly on the pixel array.

Main Results:

• Achieved high luminance (>3x10^5 cd·m⁻²) and high-speed operation (5000 Hz).
• Demonstrated in-situ image reconstruction and real-time display capabilities.
• Validated neural network inference on the pixel array, achieving 99.29% accuracy for image recognition.

Conclusions:

• The proposed in-pixel processed display architecture significantly enhances intelligent display performance.
• This approach effectively addresses latency and energy bottlenecks in edge smart systems.
• The integration of in-memory computing with micro-LED displays opens new avenues for high-performance computing and display technologies.