3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography

Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods provide 3D information but lack atomic resolution, while conventional electron microscopy offers limited depth sensitivity. Here we show how multislice electron ptychography, a computational microscopy technique with sub-Ångström lateral and nanometer-scale depth resolution, enables 3D imaging of buried device structures. We image prototype gate-all-around transistors and directly quantify roughness, strain, and defects at the interface of the 3D gate oxide wrapped around the channel. We find that silicon in the 5-nm-thick channel relaxes away from the interfaces, leaving only ~60% of atoms in a bulk-like structure. From a single dataset, ptychography provides quantitative metrology of atomic-scale interface roughness in 3D, previously accessible only through indirect inference, along with strain and other structural parameters needed for device modeling and process development.