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A Graph-based Benchmark dataset for Printed Circuit Netlist Partitioning.

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This study introduces BenchPCNP, a new dataset for printed circuit netlist partitioning. It addresses the need for labeled data to advance graph machine learning in electronic design automation.

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Area of Science:

  • Computer Science
  • Electrical Engineering
  • Machine Learning

Background:

  • Printed circuit netlist partitioning is crucial for electronic design automation and reverse engineering.
  • Graph machine learning offers new approaches, but lacks benchmark datasets.
  • Existing research faces challenges due to the absence of high-quality, labeled netlist data.

Purpose of the Study:

  • To propose a method for constructing netlist graph data in Protel 2 format.
  • To create a labeled partitioned printed circuit netlist graph dataset (BenchPCNP).
  • To provide a reliable benchmark for evaluating netlist partitioning research.

Main Methods:

  • Developed a construction method for netlist graph data.
  • Collected and partitioned 50 production-verified practical circuits following IPC-2612 standards.
  • Annotated the dataset with 54 distinct partition module labels.

Main Results:

  • Successfully created the BenchPCNP dataset.
  • The dataset contains 50 partitioned circuits with detailed annotations.
  • Offers 54 unique partition module labels for comprehensive analysis.

Conclusions:

  • BenchPCNP dataset addresses the critical need for labeled netlist data.
  • Facilitates research consistency and domain alignment in netlist partitioning.
  • Serves as a valuable benchmark for advancing graph machine learning in EDA.