A Graph-based Benchmark dataset for Printed Circuit Netlist Partitioning

As a critical component of electronic design automation and reverse engineering, printed circuit netlist partitioning has long been a significant research topic in this field. Recent advancements in graph machine learning techniques have brought new opportunities for netlist partitioning research. However, the lack of high-quality benchmark datasets with partitioning-labeled netlist data remains a major challenge. To promote research consistency and domain alignment, this paper proposes a construction method for netlist graph data in Protel 2 format and accordingly creates a labeled partitioned printed circuit netlist graph dataset-BenchPCNP. Five electronic designers followed the IPC-2612 design standards to partition 50 production-verified practical circuits, thereby constructing this dataset. The dataset covers 54 distinct partition module labels with clear module partitioning annotations, serving as a reliable performance evaluation benchmark for subsequent research.