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MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

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Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
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The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) plays a pivotal role in modern electronics thanks to its versatility and efficiency in controlling electrical currents. This device, also known as IGFET, MISFET, and MOSFET, has three main terminals: the Source, Drain, and Gate. MOSFETs are classified into n-channel or p-channel types based on the doping characteristics of their substrate and the source or drain regions.
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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
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Large-scale gate-all-around MoS2 transistor array through lossless monolithic 3D integration.

Chao Chen1,2, Kuanglei Chen1,2, Hang Zhao1,2

  • 1Academy for Advanced Interdisciplinary Science and Technology, Key Laboratory of Advanced Materials and Devices for Post-Moore Chips Ministry of Education, State Key Laboratory for Advanced Metals and Materials, University of Science and Technology Beijing, Beijing 100083, China.

National Science Review
|March 13, 2026
PubMed
Summary
This summary is machine-generated.

Researchers developed a new lossless monolithic 3D integration process for molybdenum disulfide (MoS2) gate-all-around field-effect transistors (GAAFETs). This interface engineering strategy overcomes performance degradation, enabling uniform large-scale integration of high-performance 2D material devices.

Keywords:
2D MoS2gate-all-aroundlarge scalelossless monolithic 3D integrationseed layerultrahigh current density

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Area of Science:

  • Materials Science
  • Nanotechnology
  • Electrical Engineering

Background:

  • Integrating 2D materials into 3D architectures offers advanced processing capabilities.
  • Interfacial doping during dielectric deposition degrades MoS2 3D gate-all-around (GAA) field-effect transistor (FET) performance, hindering large-scale integration.

Purpose of the Study:

  • To demonstrate a lossless monolithic 3D (M3D) integration process for MoS2 GAAFETs.
  • To overcome performance degradation caused by interfacial doping in 3D integrated devices.
  • To achieve highly uniform, large-scale integration of multichannel MoS2 GAAFETs with ultrahigh current density.

Main Methods:

  • Interface engineering strategy using van der Waals contacts with MoS2 to reduce interface states and dielectric doping.
  • Formation of hydrophilic surfaces via an Sb2O3 layer for improved high-κ dielectric deposition.
  • Fabrication and characterization of 112 MoS2 GAAFET devices.

Main Results:

  • Record-breaking average on-state current density of 227 μA/μm (peak >335 μA/μm).
  • Ideal minimum subthreshold swing approaching 60 mV/dec.
  • 46% reduction in resistance-capacitance delay compared to planar structures, confirmed by TCAD simulations.

Conclusions:

  • The developed interface engineering strategy enables lossless M3D integration of MoS2 GAAFETs.
  • This approach significantly improves GAAFET performance by minimizing interface states and dielectric doping.
  • Establishes a viable manufacturing pathway for interface-doping-free dielectric deposition in high-density M3D heterogeneous integration.