Generic logic block based on bias-gated 2D MoS₂ transistors.

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Science

Background:

• Integrating 2D semiconductors with CMOS is key for next-gen circuits.
• Challenges include limited 2D semiconductor polarity modulation and CMOS architecture constraints.

Purpose of the Study:

• To develop a novel generic logic block (GLB) for reconfigurable logic operations.
• To overcome limitations of current 2D semiconductor integration and CMOS architectures.

Main Methods:

• Utilized bias-gated molybdenum disulfide transistors (BG-FETs).
• Designed a GLB comprising four BG-FETs for reconfigurable logic.
• Cascaded GLBs to create flip-flop circuits and arithmetic logic units.

Main Results:

• BG-FETs demonstrated threshold-adaptive field-effect characteristics with bias manipulation.
• The four-BG-FET GLB achieved reconfigurable logic operations (gates, half-adder, MUX, encoder, SRAM).
• Achieved over 60% transistor count saving compared to CMOS for complex circuits.

Conclusions:

• BG-FET-based GLB offers a promising post-CMOS integration technology.
• This approach significantly reduces transistor count for complex logic functions.
• Enables efficient and reconfigurable integrated circuit designs.