Revealing and engineering contact-origin noise in ultrathin tellurium transistors

Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its strong air stability, excellent hole transport, narrow bandgap, and BEOL-integration compatibility. However, when the Te thickness approaches the depletion width, traps at the contact interface strongly affect carrier injection and introduce excess low-frequency noise. Here, we systematically investigate the origin of noise in ultrathin Te field-effect transistors (FETs) through bias- and temperature-dependent 1/f noise analysis. In devices with a 5 nm Te channel, contact-origin trap-assisted tunneling dominates in the low-current regime, producing deviations from the carrier-number-fluctuation (CNF) model at 300 K. Cooling to 100 K suppresses trap activation and restores typical CNF behavior, whereas 13 nm devices maintain CNF consistency at both temperatures due to screening of the contact region. To mitigate contact-origin noise, a locally thickened (13 nm) Te layer was inserted beneath the source and drain metal contact while preserving a 5 nm active Te channel. This design restores CNF behavior at room temperature, lowers the noise level in the nA current regime by an order of magnitude, and decreases the drain-bias dependence of noise by approximately twofold. The results identify near-contact traps as the primary noise source in ultrathin Te and demonstrate contact-centric engineering as an effective strategy to decouple device scaling from noise, enabling reliable, low-noise Te electronics.