A review of SPAD array chip design for direct time-of-flight LiDAR

As the requirements of LiDAR for data processing volume, ranging accuracy, and anti-interference capability continue to rise, significant transformations have occurred in recent years in the system architecture, data flow design, and algorithm modules of LiDAR receiver chips. This paper reviews the current design status of direct Time-of-Flight (dToF) ranging sensor chips, focusing on three key aspects for systematic summarization: first, innovations in ranging methods, covering two novel technical schemes, namely histogram-free and variable histogram resolution; second, anti-interference and accuracy optimization, including the chip's suppression of ambient light, mitigation of inter-LiDAR interference, and calibration methods for ranging accuracy; third, comprehensive design optimization of chip Power, Performance, and Area (PPA). Finally, several targeted improvement suggestions are put forward to address existing design bottlenecks, providing references for the subsequent research and development of ToF ranging sensor chips.